International Journal of Academic Research and Development

International Journal of Academic Research and Development


International Journal of Academic Research and Development
International Journal of Academic Research and Development
Vol. 1, Issue 2 (2016)

Layout designing of full adder with minimum number of transistors using 32nm CMOS technology


Rita Rani

Full Adders are the basic and very important component of every circuit and microprocessors. In this paper an efficient and new way of designing the full adders is proposed. Full adder is designed so as to reduce the power consumption and the chip area occupied by it. The proposed design uses 8 Transistors. It is fulfilled by using 2 XNOR (3T+3T) gates and one 2X1 MUX (2T). There are two layouts which have been discussed in this paper. One is auto generated layout and another is customized layout. Both the layouts are compared by taking different parameters like Surf area, power consumption and delay.
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